FPGA Implementation of a Modified Hard Decision Decoding for 2-D TPC

摘要

A modified algorithm for two-dimensional TPC decoding is proposed to reduce the wrong frame rate in the (16,11,4)~2 Turbo Product Code (TPC) decoding in this paper. It is based on the hard decision decoding, including a chooser and a parallel decoding architecture that one is column-row and the other is row-column. The Monte-Carlo simulation shows that 30% wrong frame is eliminated and the implementation of the decoder for TPC (16,11,4)~2 with FPGA has achieved the decoding throughput of 53Mbit/s with 20M clock.