When transposing large matrices using SDRAM memories, typically a control overhead significantly reduces the data throughput. In this paper, a new address mapping scheme is introduced, taking advantage of multiple banks and burst capabilities of modern SDRAMs. Other address mapping strategies minimize the total number of SDRAM page-opens while traversing the two-dimensional index-space in row or column direction. The new approach uses bank interleaving methods to hide wait cycles, caused by page-opens. In this way, data bus wait cycles do not depend on the overall number of page-opens directly. It is shown, that the data bus utilization can be increased significantly, in particular, if memories are accessed with parallel samples. Therefore, double buffering can be omitted. As a special operation, 2D-FFT processing for radar applications is considered. Depending on SDRAM parameters and dimensions, a continuous bandwidth utilization of 96 to 98% is achieved for accesses in both matrix directions, including all refresh commands.
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