A novel methodology for testing all digital systems fused onto the FPGA has been developed in this paper. This methodology does not require any hook-up and Input/Output (I/O) interfacing card. This methodology uses the NIOS processor core to configure system onto the FPGA. HDL code of the digital system along with NIOS core is downloaded onto the FPGA. The NIOS processor can be programmed, to supply all possible combinations of test vectors to the digital system and read back the results generated by the digital system. The results are compared with the expected results on the NIOS processor and the errors displayed. After studying the error, the HDL code is tuned and the process is repeated till getting zero error. Once the process is completed, either the HDL code of the tested digital system or macro of the tested digital system can be a physically proven digital system. The advantage of this methodology is that, high throughput of the digital systems can be verified; by considering that NIOS II frequency is adequate to supply the test vectors. By the way, the time required to verify the digital system with all possible combinations of test vectors is greatly reduced.
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