Selective attention is a process widely used by biological sensory systems to overcome the problem of limited parallel processing capacity: salient subregions of the input stimuli are serially processed, while non-salient regions are suppressed. We present an analog Very Large Scale Integration implementation of a building block for a multi-chip neuromorphic hardware model of selective attention. We describe the chip's architecture underlining the similarity between the circuits and biological neurons and synapses. We plan to present experimental results that explore the dynamics of the system varying its bias settings corresponding to physiological properties of neurons and synapses.
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