Hardware Accelerator for Differentiable Neural Computer and Its FPGA Implementation

摘要

Along with the recent progress of deep artificial neural network (DNN) research, accelerator circuits aiming at high speed of DNN has been proposed. These are dedicated for conventional multilayer DNNs so that they are lack of efficiency to execute a newly proposed neural network such as Differentiable Neural Computer (DNC). Since the DNC is composed of a long-term short-term memory (LSTM) and an external memory, it is necessary to calculation of the LSTM and reading/writing operations high speed to the external memory. In this research, a pipelined accelerator is studied in order to execute a weighted sum and its non-linear activation function by a single instruction. In this accelerator, input data and weights stored in each SRAM module fetched, and them is multiplied and accumulated consecutively. The final resultant data is written back into the SRAM module. It is designed for Stratix V, Intel FPGA chip, and the performance evaluation was carried out.