Interconnect delay begins to dominate overall device delay at 180 nm, making low resistivity copper highly desirable. Copper migrates very quickly in silicon; therefore, successful integration requires stringent control of copper cross-contamination from deposition equipment, electroplating tools, chemical-mechanical polishing (CMP) equipment, and all metrology tools shared by copper processed wafers. In this paper, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm - 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ spin-process contamination elimination (SpCE) clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality.
展开▼
