Totally self-checking FSM design based on multilevel synthesis methods and FPGA implementation

摘要

Achieving acceptable reliability level for VLSI is one of the most critical issues that need to be faced. On-line testing techniques development is applicable solution of the problem. For this aim it is necessary to engineer cost effective self-checking VLSI circuits with using the proper CAD tools. It is profitable to elaborate such tools using suitable non self-checking design tools that have been just developed In this paper we research FSM self-checking design abilities for ROBDD or free BDD with using LUT based FPGA technology. It is established that direct covering ROBDD (free BDD) with CLBs provides a unidirectional manifestation of faults resulted from FPGA technology. We also suggest a self-checking (m,n) code checker implementation oriented to FPGA technology.