首页> 外文会议>International conference on ASIC >LS MPP Microprocessor Design for I_DDQ Testability
【24h】

LS MPP Microprocessor Design for I_DDQ Testability

机译:LS MPP微处理器设计I_DDQ可测试性

获取原文

摘要

I_DDQ testing is an effective method for detecting CMOS various defects. However, the applicability of this technique requires careful examination. The basic principle of design for I_DDQ testability is to eliminate high current states from the design. If there is high background current during the I_DDQ test, defects can be masked or good chips can be marked as bad. In this paper, firstly, we analyze the circuit which cause high current states in LS MPP microprocessor, then we given some solutions to eliminate high current states in the design.
机译:I_DDQ测试是检测CMOS各种缺陷的有效方法。然而,这种技术的适用性需要仔细检查。 I_DDQ可测试性设计的基本原理是消除设计中的高电流状态。如果在I_DDQ测试期间有高背景电流,则可以屏蔽缺陷或良好的芯片可以标记为坏。在本文中,我们分析了在LS MPP微处理器中引起高电流状态的电路,然后我们给出了一些解决方案来消除设计中的高电流状态。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号