A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs

摘要

Performance of system-on-chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasisynchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18//spl mu/m technology.