Off-line testing of asynchronous circuits

摘要

A new technique to test asynchronous circuits obtained by direct mapping technique from I-safe Petri nets is proposed. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into high-level specification, a Petri net. A "pseudo clock" is used to handle hazards and activate faults which exhibit themselves only under particular arrangements. Asynchronous circuit obtained by direct mapping technique can be made 100% testable for stuck-at-faults by implementing testability features. An algorithm to insert testability features and generate test sequences is presented using a benchmark.