Low Complexity Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable Feature

摘要

In this present era of high speed developing world of VLSI, data comparison is broadly used in computing system. In a computation system the receiving data needed to compare with deposited information to trace the identical entry. Comparison of data is a technique which fetches data together from various sources and compares it. When this matching differ the stored data, the use of proprietary matching algorithms is used to compare and correct the mismatch result. As per the survey, different researches have been done and still going on till date. In this study, it is found that the data matching can be done both in encoder and decoder end. The kept data preserved through error correcting codes (ECC code word) is used to relate with arriving data after decryption. Furthermore, in a Renovated butterfly weighted accumulator (BWAR), a type of reversible logic gate called peres gate is proposed to modify the half adder with disparate algorithm to compute hamming distance with reduced complexity and improved efficiency with testable feature. For a ECC code (16, 11) the proposed BWAR architecture minimizes the hardware complexity by 30.4% approximately with 13% of improved efficiency. In this brief, we have used a Xilinx 13.2 for Verilog coding for data matching algorithm.