An efficient building block layout methodology for compact placement

摘要

In this paper, a new efficient methodology for building block layout is presented by using synthesis placement and compaction. The synthesis placement part of the methodology is based on a formal language called GEOMETRIA. The compaction part is based on geometric reshapings (gs) of blocks and the merging of the communication channels. Both reshaping and merging follow the VLSI regulations for legal layout placement and improve the overall functional performance of the integrated system, by reducing the average length of the connection lines and the size of the occupied chip area by retaining the functionality and the neighboring relations of the blocks. The main goal of the blocks' geometric reshaping is minimization of the wasted area (or dead space among the blocks) called "open holes". The channels merging process of compaction is based on the legal overlapping of the blocks' communication channels by reducing the layout placement at the local and global routing.