A novel single flux quantum speed conversion buffer for the internal speedup architecture

摘要

Internal speedup architecture is a very useful approach to increase system performance. A single flux quantum circuit, which can operate at a speed 10 times higher than that of the fastest CMOS circuits, is suitable for use with this architecture. To realize this architecture in a system, a speed conversion interface is required. We proposed a new speed conversion method and designed a speed conversion circuit that converts serial bit streams from 10 to 40 Gbps. This circuit consists of stream demultiplexers, stream multiplexers and shift registers. We designed a physical layout of the stream demultiplexer and confirmed correct 10 GHz operations by simulations. As a demonstration, we fabricated a critical part of the stream demultiplexer and confirmed that it operated correctly.