The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies. Some necessary and sufficient conditions for imposing the inclusion property for fully-associative and set-associative caches, which allow different block sizes at different levels of the hierarchy, are given. Three multiprocessor structures with a two-level cache hierarchy (single cache extension, multiport second-level cache, and bus-based) are examined. The feasibility of imposing the inclusion property in these structures is discussed. This leads to the presentation of an inclusion-coherence mechanism for two-level bus-based architectures.
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