Folded Cascode Current Mirror Design using Cadence

摘要

With an increasing demand for analog integrated devices, the use of current mirror circuits has witnessed an unprecedented surge. By having very high output impedances, these devices are able to deliver constant current and work as active loads. A significant variation of these current mirrors is a folded cascode configuration, derived from the regular cascode configuration. The folded cascode configuration utilizes a dual pnp-npn network to provide current feedback and thus displays a superior output impedance, a very large impedance-bandwidth and improved current tracking. The results of the folded cascode current mirror simulation obtained using Multisim are verified using Cadence, a more accurate EDA software. This paper highlights the theoretical framework for the operation of current mirror devices and delves into the properties of the folded cascode current mirror. It expounds the simulated results obtained through Cadence, performs a comparison between the results of the two software and concludes by discussing the circuit's future prospects.