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An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems

机译:暗硅异构系统中电力绩效意识的加速器/核心分配挑战的调查

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Although the power density is said to be constant according to Dennard Scaling Model, the energy efficiency has not scaled along in the last decade. With increase in integration of transistors, the power budget is no longer balanced while moving from one technology node to another. Because of this the power density is no longer constant and it is now increasing with technology scaling. In successive generations the percentage of chip that can be switched at full frequency is dropping exponentially. This problem of Dark Silicon [1] is forcing the designers to power on only a few on-chip resources [2] at a time in order to avoid hitting the maximum power utilization mark. If we keep neglecting the Power density issue it is said that the microprocessors will soon have power density comparable to that of the sun at around 10,000W/cm2. Heterogeneous computing [3] is one of the proposed solutions to effectively tackle the power problem with increasing number of transistors. It has been crucial in increasing the performance and energy efficiency. A Heterogeneous Architecture has the potential to match each application to the best suited core. In Heterogeneous Architectures, each application can be matched to the best suited core in order to efficiently run the application. This solves the problem where most applications under utilize the hardware and there is very little performance drop when the same application is run on a less powerful processor. Dark Silicon also opens up new possibilities for integrating Hardware Accelerators which can be scheduled dynamically or statically. In Heterogeneous systems, the large number of exchanges between cores also contribute to the increase in power consumption. The interconnects also play an important role in energy efficiency. This paper focuses on identifying and highlighting some of the critical challenges faced due to Dark Silicon. The paper also lists down some initial research efforts to tackle these issues.
机译:尽管据说功率密度常数根据丹尼德缩放模型,但是能效在过去十年中没有缩放。随着晶体管集成的增加,电源预算不再平衡,同时从一个技术节点移动到另一个技术。因此,功率密度不再是恒定的,现在通过技术缩放现在增加。在连续几代中,可以以全频率切换的芯片的百分比是指数级滴定的。这种暗硅的这个问题是迫使设计人员一次电动电源,以避免击中最大电力利用标记。如果我们忽略忽略电力密度问题,则表示微处理器很快将具有与太阳相比的功率密度约为10,000W / cm2。异构计算[3]是越来越多的晶体管有效地解决功率问题的解决方案之一。提高性能和能源效率至关重要。异构架构有可能将每个应用程序匹配到最适合的核心。在异构架构中,每个应用程序可以与最适合的核心匹配,以便有效运行应用程序。这解决了在使用硬件的大多数应用程序和在不太强大的处理器上运行时的性能下降的问题,因此解决了问题。暗硅还开辟了整合硬件加速器的新可能性,该硬件加速器可以动态地或静态地安排。在异构系统中,核之间的大量交换也有助于功耗的增加。互连也在能效起到重要作用。本文重点介绍并突出显示由于暗硅因暗硅而面临的一些关键挑战。本文还列出了解决这些问题的一些初步研究工作。

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