Design of On-Chip Debug System for embedded processor

摘要

In this paper, we introduce On-Chip Debug System (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (On-Chip Debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG (Joint Test Action Group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.