The speed of a multiplier is of utmost importance to any Digital Signal Processor (DSPs). Along with the speed its precision also plays a major role. Although Floating point multipliers provide required precision they tend to consume more silicon area and are relatively slower compared to fixed point (Q-format) multipliers. In this paper we propose a method for fast fixed point signed multiplication based on Urdhava Tiryakbhyam method of Vedic mathematics. The coding is done for 16 bit (Q15) and 32 bit (Q31) fractional fixed point multiplications using Verilog and synthesized using Xilinx ISE version 12.2. Further the speed comparison of this multiplier with normal booth multiplier and Xilinx LogiCore parallel multiplier Intellectual Property (IP) is presented. The results clearly indicate that Urdhava Tiryakbhyam can have a great impact on improving the speed of Digital Signal Processors.
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