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Fast Copper Plating Process for Through Silicon Via (TSV) Filling

机译:硅通孔(TSV)填充的快速镀铜工艺

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There is an increasing demand for electronic devices with smaller sizes, higher performance and increased functionality. The development of vertical interconnects or through silicon vias (TSV) may be one of the most promising approaches to provide the three-dimensional (3D) integration of integrated circuits (IC). It is possible to improve the system's performance with shorter RC delay, shorter signal paths and less power consumption. Electroplating process is one of the major contributors to the cost of TSV. Thus, plating time is one of our major concerns in TSV applications. About 80% of the TSVs are filled with copper due to its high conductivity and wide applications in multilayer wiring. Even though the electroplating of copper for interconnections is well established for the copper damascene micro-fabrication process, it has been shown that the filling of TSVs with copper plating is a different situation due to the much larger dimensions of TSVs. Generally the filling mechanism consists of conformal plating and bottom up plating. A 100% bottom up filling is preferred for copper filling in TSV. A seam may exist in via if the majority of filling mechanism is conformal plating. Thus, the bottom up filling profile is one the critical points to achieve void free filling. In this study, the void free copper filling TSVs with diameter from 10-30 m and depth from 50-150 m will be investigated by copper electroplating. A near 100% bottom up plating formula was developed in order to achieve void free and seam free filling. Filling performance of this plating formula was evaluated by examining vertical cross-sections and top-down cross-section of the filled TSVs using optical microscope and X-ray method. Pretreatment process and relationship with diffusion time will be also studied with respect to the TSV plating process. The effect of concentration of copper, acid and additives will be optimized to achieve the desired bottom up plating process. The ultimate goal is to achieve TSV plating with shorter plating time and better consistency. Electroplating experiment was conducted with an industrial electroplating tool. Successful plating results are demonstrated with optimized plating bath and plating mechanism. The void free and seam free copper deposition results are shown with minimized overburden. The time taken for the plating process is also greatly reduced with this near 100% bottom up plating formula. The benefits of this novel plating mechanism will be discussed in detail in this paper.
机译:对具有更小尺寸,更高性能和更多功能的电子设备的需求不断增长。垂直互连或硅通孔(TSV)的开发可能是提供集成电路(IC)的三维(3D)集成的最有前途的方法之一。较短的RC延迟,较短的信号路径和较少的功耗可以改善系统的性能。电镀工艺是造成TSV成本的主要因素之一。因此,电镀时间是我们在TSV应用中的主要问题之一。由于其高导电性和在多层布线中的广泛应用,大约80%的TSV被铜填充。即使对于铜镶嵌微制造工艺而言,已经很好地建立了用于互连的电镀铜,但是已经表明,由于TSV的尺寸要大得多,因此用铜电镀填充TSV的情况是不同的。通常,填充机制包括保形电镀和自底向上电镀。对于TSV中的铜填充,最好使用100%自下而上的填充。如果大多数填充机制是保形电镀,则通孔中可能存在接缝。因此,自下而上的填充轮廓是实现无空隙填充的关键点之一。在这项研究中,将通过电镀铜来研究直径为10-30 m,深度为50-150 m的无空隙铜填充TSV。开发了一种接近100%的自底向上电镀配方,以实现无空隙和无接缝的填充。通过使用光学显微镜和X射线方法检查填充的TSV的垂直横截面和自上而下的横截面来评估该镀覆配方的填充性能。对于TSV电镀工艺,还将研究预处理工艺及其与扩散时间的关系。铜,酸和添加剂的浓度影响将得到优化,以实现所需的自下而上的电镀工艺。最终目标是实现具有更短电镀时间和更好一致性的TSV电镀。用工业电镀工具进行电镀实验。优化的电镀液和电镀机理证明了成功的电镀结果。显示出无空隙和无接缝的铜沉积结果,并具有最小的覆盖层。使用这种接近100%的自底向上电镀配方,电镀过程所需的时间也大大减少。本文将详细讨论这种新颖的电镀机制的好处。

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