High speed asynchronous ADC in CAD mentor graphics AMS 0,35 µm CMOS

摘要

This paper contains the asynchronous ADC design specification which has high speed and low power. Asynchronous ADC consists of 3 blocks of units composer OP-AMP, Digital Logic and Switch Capacitor. Needs high-speed ADC is needed to convert analog signals to digital which is applied to a multimedia device, especially for video signal applications. Low power consumption is useful for efficient power use. The method used in the design is an experiment with simulation CAD software mentor graphics technology with technology CMOS of AMS (Austria Micro Systems) 0.35 µm. Stage design is the A-ADC circuit design with simulation results. The end result is to obtain a design prototype A-3-bits ADC, power consumption <15mW and voltage 3.3 V. CT