A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (Rc) of 8.0×10−10 Ω·cm2 and the electrode''s sheet resistance (Rsheet) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi2 and W/Pd2Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.
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