A key factor for the propagation of technological applications is the miniaturization of respective components, subsystems and overall systems. To meet future requirements in such size decreasing environments the packaging and mounting technology needs new impulses. 3D-MIDs (three-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. A three-dimensional shaped circuit carrier allows the integration of various functional features (e.g. electrical connections, housing, thermal management, mechanical support). This combination makes a further system shrinking possible. Yet, the mounting of high-density area-array fine-pitch packaged semiconductors (BGA, CSP, MCM) or bare dies to 3D-MIDs is problematic. The lack of a three-dimensional multilayer technology makes a collision free escape routing for devices with a high I/O count difficult. Therefore a new 3D-MID multilayer process was developed and combined with an established 3D-MID metallization process. A demonstrator with three metallization layers, capable, e.g., for flip-chip mounting of area-array packages, is fabricated. The multilayer structure of the demonstrator is investigated with respect to the mechanical and electrical behavior.
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