Model based CAOPC flow for memory chips to improve performance and consistency of RET solutions

摘要

Key factors for maximizing yield in a modern semiconductor fab for Memory device manufacturing include wafer critical dimension uniformity and accuracy control. Resolution Enhancement Techniques (RET) solutions for the highly repetitive arrayed memory devices have been driven by the need for perfect geometric consistency without compromising the lithographic quality. Traditionally, both optical proximity correction (OPC) and sub-resolution assist features (SRAFs) insertion for these repetitive cell-array structures have been dealt by applying manual hand-crafted or rule-based methods. But these can be prone to iterative human intervention, long runtimes and sub-par lithographic quality. This work adopts a pattern/property aware approach (PA)2 and cell-array OPC technology that leverage the inherent repetitive and hierarchical structure of the cell-array to ensure the lithographic quality and perfect geometric consistency and symmetry down to the level of feature edges with model-based OPC and rule-based SRAF solutions. The flow also demonstrates a drastic reduction in runtime and turn-around-time to mask tapeouts for the full chip (core and periphery).