The Design of Digital Sub-array Synchronization for Phased Array Radar

摘要

Digital sub-array synchronization is a key problem in phased array radar design. The sampling rate of ADC and DAC is a decisive index to determine the difficulty of synchronization. This paper discusses the synchronization between multi-chip ADC with 1Ghz sampling rate and DAC converter with 2.5ghz sampling rate. The key to synchronization is how to meet the timing deviation requirements of jesd204b-1 protocol for the SYSREF signal arriving at each converter. In this paper, an innovative feedback mode is adopted to adjust the signal timing sequence actively to achieve the effect of accurate synchronization, and then the design and implementation of phase array radar digital sub-array stage synchronization under high sampling rate is realized.