A Divide-by-4 and −8 Circuit for 77 GHz Radar in 22 nm FD-SOI CMOS

摘要

A divider circuit with selectable divide ratio, by 4 and 8, is designed in the 22 nm FD-SOI CMOS of GLOBALFOUNDRIES. Its application is in 77 GHz radar chirp generation, as pre-scaler from the voltage controlled oscillator (VCO) working at half frequency (37 to 41 GHz). A combination of extended true-phase single clock (ETSPC) and TSPC architecture is used for the divider cell. The pre-scaler realizes a singleended to differential signal conversion as well. Measurements are performed at supply voltages between 0.8 and 1.6 V. The divider can work between 10 and 64 GHz with sensitivities better than −30 dBm around the targeted frequency range of the VCO. DC power consumption is 2.2 mW for a single divider cell while the complete pre-scaler system needs 27 mW at 0.8 V supply.