首页> 外文会议>International Microsystems, Packaging, Assembly and Circuits Technology Conference >Advanced Channel Analysis Method using Channel Quality Comparison and Design of Experiments
【24h】

Advanced Channel Analysis Method using Channel Quality Comparison and Design of Experiments

机译:利用渠道质量比较和实验设计的先进渠道分析方法

获取原文

摘要

The design phases of a sever product are often very long. It often takes average one and half years from feasibility study phase to mass production. The layout period is also usually at least one month due to larger board size and routing complexity. Although layout period is long, the arranged design review time is still limited. SI simulation and analysis method plays the important role in the design review phase.Channel Quality Check (CQC) is Intel channel analysis method with very high accuracy from PCB. CQC [1] [2] [3] is well-adopted by Intel customers during their high speed differential buses and memory channel designs. CQC can help system designers to check their channel designs are better or worse than a reference design or a specification from Intel. With just a few simulation cases in CQC methodology, OEM/ODM SI engineers can save tremendous simulation time in doing risk assessment of their designs but still keeping high simulation confidence level. However, CQC won't give too much channel manufacture variation information.Units per Million (UPM) is also Intel channel analysis method. UPM first uses Design of Experiment (DOE) to scan manufacture variation and Response Surface Modeling (RSM) to form models of manufacture variation. UPM can be obtained by millions simulations using the models. UPM can provide vast information regarding all manufacture variations. The information may help engineers to make goo go decision based on their own experience and engineering judgement. So some OEM/ODM SI engineers also use this method to do hundred to thousand SI simulations for their critical or challengeable products although it will spend much simulation time.However, comparing with PCB variables, the accuracy of variables of silicon and package designs are much less accurate due to extremely complicated silicon design. Therefore PCB board designers prefer to focus on the analysis of PCB variables rather than considering inaccurate silicon variables as well if possible.
机译:服务器产品的设计阶段通常很长。从可行性研究阶段到批量生产通常平均需要一年半的时间。由于更大的电路板尺寸和布线复杂性,布局周期通常也至少为一个月。尽管布局周期长,但是安排的设计评审时间仍然有限。 SI仿真和分析方法在设计审查阶段起着重要作用。通道质量检查(CQC)是来自PCB的具有很高准确性的Intel通道分析方法。 CQC [1] [2] [3]在英特尔客户的高速差分总线和内存通道设计中得到了广泛采用。与英特尔的参考设计或规范相比,CQC可以帮助系统设计人员检查其通道设计的优劣。通过CQC方法论中的少数几个模拟案例,OEM / ODM SI工程师可以在进行设计风险评估时节省大量模拟时间,但仍保持较高的模拟置信度。但是,CQC不会提供太多渠道制造变化信息。每百万单位(UPM)也是Intel渠道分析方法。芬欧汇川首先使用实验设计(DOE)来扫描制造变化,并使用响应面建模(RSM)来形成制造变化模型。使用该模型,可以通过数百万次仿真来获得UPM。芬欧汇川可提供有关所有制造变化的大量信息。该信息可以帮助工程师根据他们自己的经验和工程判断来决定是否通过。因此,一些OEM / ODM SI工程师也使用此方法对其关键或具有挑战性的产品进行了数百至数千次SI仿真,尽管这会花费大量的仿真时间。但是,与PCB变量相比,硅和封装设计变量的准确性非常高由于硅设计极为复杂,因此精度较低。因此,PCB板设计人员更喜欢专注于PCB变量的分析,而不是尽可能考虑不准确的硅变量。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号