Tiny Passive Chip 008004 and 5μm HD SMT Process Development (IMPACT 2018)

摘要

Miniaturization is a way to make product smaller, thinner and lighter. Designer can put more components on the same layout area to have more functions or reduce the PCBA (Printed Circuit Board Assembly) size via miniaturization technology. So USI keeps studying advanced process to fulfill higher layout density requirement in future products. Basically, there are two ways to achieve the goal of miniaturization. One is to place smaller component on the board ; the other one is to raise the layout density (place smaller component clearance). USI did both of them. As mobile devices such as smartphones gain more functions and improve performance continuously, so that there is a requirement for more compact components in order to fit more of them on the present layout area, or even smaller. Meanwhile, wearable devices are getting more and more popular, and it also creates increased demand for more compact components. Passive chip 008004” (0.250 mm × 0.125 mm, 60% area smaller than 01005”) is the world's smallest passive (not mass production application yet in the world). USI started to study the SMT (Surface Mount Technology) process of passive 008004” from Y2014 and got the whole process (SMT + Molding) ready in Y2017. As for the high density (HD) SMT, USI keeps to study the advanced SMT process in order to fit smaller component clearance consistently, including equipment, material, method and recipe study. Two steps of SMT process development were implemented for passive chip 008004“ and HD SMT design. Footprint selection was the major purpose of step#1, USI collected the footprint design proposals from vendors and USI internal, then got footprint designs with better SMT yield rate into step#2. Process recipe optimization and reliability verification are the two major purposes in step#2. In the step#1 study, USI place the 008004“~0402“ passive chips only with 76μm (3mil) and 102μm (4mil) component clearance, but not include active components to verify the passive footprint design. Then consider the molding process verification and reliability qualification into the step#2 design to verify whole process. The step#2 test vehicle are designed with active components to approach the components composition of a wifi module and then lay the components in smaller component cleanance 70μm, 65μm and 50μm on it than step#1. In previous process development, we step over the limitation in stencil thickness (replacing 40μm with 50μm) and printing solder paste powder size (replacing Type6 with Type5) to reach the same printing quality as current POR (Plan Of Record), 50μm + Type5, in wifi modue. In the step#2 study, we have to find a better recipe for mass production since 40μm stencil thinkness is not good for other larger compoents and Type6 solder paste is more expensive than Type5. The test vehicle of step#2 with molding passed the TC850/TH1000/uHAST264 without solder joint strength related failure. The development can be a good start for a real product to implement the next generation HD SMT design.