A Simple and Practical Statistical Device Model for Analog LSI Designs

摘要

With the scaling of CMOS devices toward their ultimate dimensions, device performance variability induced by process variation has become a critical issue in analog LSI designs. Statistical device model library building based on statistical device model considering the process variation accurately is useful to predict the performance of analog LSI designs. However, conventional statistical device models are either complicated or not accurate enough. Therefore, a simple and practical statistical device model for analog LSI designs is proposed in this paper. Simultaneously, a simple method to extract model parameters is also proposed. Statistical analysis results of 0.65μm CMOS Op-Amp based on the proposed model using Monte Carlo simulation have a good agreement with the chip measurement results.