Design of Fault Tolerant Multiplier Using Self checking adder and GDI Technique

摘要

Fault tolerance plays an essential role in much safety-critical application for the system to work correctly during the occurrence of faults. In this system, processing units play a crucial role but they are more sensitive to faults due to their smaller size. Hence, this paper is focused on designing 4- bit multiplier utilizing a fault-tolerant one-bit full adder circuit which can identify and repair both transient and permanent faults. Fault-tolerant one-bit full adder is designed using self- checking adder circuit to check any fault and repairing circuit to repair the fault. Further, the utilization of the GDI (Gate Diffusion Input) technique reduces the number of transistors is utilized contrasted with regular full adder circuit thereby reducing the area, power, and delay utilization. This design brings about much lower equipment when compared to the conventional methods. Moreover, the proposed method gives both error detection and correction effectively when contrasted with the current designs.