Integrated Test Structures for Reliability Investigation under Dynamic Stimuli

摘要

Reliability for advanced CMOS nodes is becoming very challenging. Static stress may not be sufficient to understand digital circuit reliability in case of transient and frequency effect. For NBTI mechanism, it is known that projection end-of-life degradation based on DC stress is pessimistic and thus poorly accurate. This paper presents dedicated test structures to evaluate different wear-out mechanisms under dynamic stimuli. Firstly, oxide breakdown is investigated with 1GHz AC signal generated by a ring oscillator. Post-breakdown devices characteristics are significantly different between static and dynamic stress. Then, with another structure, the effect of hot carrier is shown in data path with different duty cycles and frequencies. Finally, a built-in V_(th) measurement structure is developed to investigate the negative bias temperature instability. It was measured that dynamic stimuli results in a different degradation magnitude than DC or low frequency one.