Study and Analysis of a 0.18 μm Single-ended Inductively-degenerated Common-source Cascode LNA Under Post-layout Corner Conditions

摘要

This paper is on the study and analysis of the effects of corner conditions and post-layout simulations performed on a single-ended inductively degenerated common-source (CS) cascode LNA at nominal 2.14 GHz frequency. 2.14 GHz is the center frequency of the W-CDMA reception range of 2.11 GHz to 2.17 GHz. This paper gives detailed explanation on the reasons for the behavior of the LNA under extreme conditions, as well as on the results of the post-layout simulations as opposed to the pre-layout simulations, which are normally absent in most of the papers describing analog designs. In this work, the LNA was designed in Silterra 0.18-μm 6-metal 1-poly RFMOS process technology. The corner conditions were provided by Silterra in its models library. The post-layout simulations were conducted using Calibre. The transistors' size in the LNA were designed using power constrained noise optimization method and the width found to be 290 μm. On-chip inductors with Q of 8 were utilized to resonate with the metal-insulator-metal capacitors (mimcap). The input was 50 Ω matched using the transistor as well as an inductor at the input and three 1.65 nH inductors connected in parallel to provide a 0.55 nH inductance at the source of the CS transistor. The LNA consumed 3.8 mA of current at a supply voltage of 1.8 V. In this work, the resistance-parasitic capacitors-coupling capacitors (RCC) had been included in the post-layout simulations performed. RCC would reflect the performance of the LNA more realistically as it includes resistive and capacitive parasitics practically existing along and between the metals and substrate. The results in this paper show that the post-layout is able to closely represent the performance of the measured LNA in majority of its simulations as compared to the pre-layout simulations. This is because the post-layout simulation includes the parasitic effects of the substrate. In conjunction with this, simulations performed on the LNA under various corner conditions provide indications on what may happen in the "real world". 10 corner conditions were imposed on the design, with variations in the device, resistors and capacitors parameters. WNWP with maximum resistance and minimum capacitance condition gave the worst gain performance and, hence, was chosen as the condition for running the noise and s-parameters simulations on the LNA. It is also shown in this paper that the absence of a large capacitor to isolate V{sub}(DD) from ground could prevent the LNA from behaving like an amplifier.