Successful void free gap fill of 3#x00B5;m, high AR via middle, Through Silicon Vias at wafer level

摘要

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3µm top entrant critical dimension (CD) and 50µm depth. Higher AR TSV integration is explored due to the lower stress influence of TSVs observed in adjacent CMOS devices. [1]