Tristate Inverter Array: A new test structure that compliments traditional SRAM arrays as a yield learning vehicle

摘要

The SRAM bitcell array has been traditionally used as a yield learning vehicle for new technologies. However, the yield of the SRAM bitcell is susceptible to parametric variations and subtle process defects/ variations. In this work a new functional array called the Tristated Inverter Array (TIA) is discussed which is much less susceptible to both parametric variation and subtle process defects while retaining all the useful features of the SRAM array (fail mappability, ease of isolation of fails, regular design). This structure can be used very effectively in yield learning as a complimentary test structure to the SRAM array for learning hard process defects.