Revisiting the Newton-Raphson Iterative Method for Decimal Division

摘要

In this paper, we propose an iterative decimal divider. The divider uses the Newton-Raphson iterative method with an initial approximation calculated with a minimax polynomial and is able to use binary multipliers. The proposed circuits were implemented in an FPGA and compared with alternative state-of-the-art solutions. The results indicate that the proposed divider is very competitive in terms of area and latency and better in terms of throughput when compared to decimal dividers based on digit-recurrence algorithms.