A 5-bit, 87-fs Step, Constant-Slope, Charge-Sharing-Based Encoding Digital-to-Time Converter in 130nm CMOS

摘要

This paper presents a new method to realize a 5 bit digital-to-time converter (DTC), in which constant-slope charging has been used. It also proposes a new structure, using a charge-sharing-based encoding and an ingenious timing to generate different start voltages to control the delay of the circuit, which greatly reduces power consumption. The DTC mentioned has been implemented in standard 130nm CMOS, achieving 87fs fine resolution when running at 50MHz, and consumes about 0.2 μ W. Differential nonlinearity (DNL) and integral nonlinearity (INL) are below 0.18LSB and 0.23LSB, respectively.