Novel chip stacking process for 3D integration

摘要

A chip stacking process for three dimensional integration is reported. This process consists of solderless thermo-compression bonding and chemical plating to connect non-contacted Cu interconnection. The Cu bumps and micro stud structures are fabricated at top and bottom chips, respectively. The optimization of themo-compression bonding, followed by chemical plating is investigated. The optimized parameters obtained for thermo-compression bonding are bonding force, temperature, and time of 15kg, 350°C, and 60sec, respectively. It is found that Ni electroless plating can compensate the high variation produced by the combination of Cu bump and micro stud structure formation, which is confirmed by daisy chain electrical resistance measurement. Furthermore, Ni electroless plating can reduce the bump electrical resistance up to 15%.