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Universal logic modules based on double-gate carbon nanotube transistors

机译:基于双栅极碳纳米管晶体管的通用逻辑模块

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Double-gate carbon nanotube field-effect transistors (DG-CNTFETs) can be controlled in the field to be either n-type or p-type through an extra polarity gate. This results in an embedded XOR behavior, which has inspired several novel circuit designs and architectures. This work makes the following contributions. First, we propose an accurate and efficient semi-classical modeling approach to realize the first SPICE-compatible model for circuit design and optimization of DG-CNTFETs. Second, we design and optimize universal logic modules (ULMs) in two circuit styles based on DG-CNTFETs. The proposed ULMs can leverage the full potential of the embedded XOR through the FPGA-centric lookup table optimization flow. Further, we demonstrate that DG-CNTFET ULMs in the double pass-transistor logic style, which inherently produces dual-rail outputs with balanced delay, are faster than DG-CNTFET circuits in the conventional single-rail static logic style that relies on explicit input inversion. On average across 12 benchmarks, the proposed dual-rail ULMs outperform the best DG-CNTFET fabrics based on tiling patterns by 37%, 12%, and 33% in area, delay, and total power, respectively.
机译:双栅碳纳米管场效应晶体管(DG-CNTFET)可以通过额外极性的栅极在场中控制为n型或p型。这导致嵌入式XOR行为,这启发了几种新颖的电路设计和架构。这项工作做出了以下贡献。首先,我们提出一种准确高效的半经典建模方法,以实现第一个与SPICE兼容的模型,用于DG-CNTFET的电路设计和优化。其次,我们基于DG-CNTFET设计和优化两种电路样式的通用逻辑模块(ULM)。所提出的ULM可以通过以FPGA为中心的查找表优化流程来充分利用嵌入式XOR的全部潜能。此外,我们证明了双通道晶体管逻辑样式的DG-CNTFET ULM固有地产生具有平衡延迟的双轨输出,比依赖于显式输入的常规单轨静态逻辑样式的DG-CNTFET电路要快。反转。根据平铺模式,建议的双轨ULM平均在12个基准测试方面的性能优于最佳DG-CNTFET织物,分别在面积,延迟和总功率方面分别达到37%,12%和33%。

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