A holistic approach for statistical SRAM analysis

摘要

We present a new method and its implementation that enables design-phase assessment of statistical performance metrics of semiconductor memories under random local and global process variations. Engineers use the tool to reduce design margins and to maximize parametric yield. Results on industry grade 45nm SRAM designs show that this holistic approach is significantly more accurate than the alternatives based on global corners or critical path netlist, which can lead to unexpected yield loss.