Design and Implementation of Efficient VLSI Architectures for Full-search Block-matching Motion Estimation

摘要

In order to generate texture motion vectors of full pixel resolution for MPEG-4 AS profile video encoding in real-time, efficient motion estimation architectures using the full search block-matching algorithm are proposed in this paper. To improve the data reuse efficiency of search area pixel, a multi-port matching scheme for pixel data buffer and transmission from search area local memory to the 2-dimensional systolic array is presented, which provides the advantage of reducing the bandwidth of the search area memory without sacrificing the processor utilization. To enhance the computing efficiency of the array architecture, the motion estimation processor employs a double clock strategy to eliminate unnecessary computation, which achieves 74.9% processing element utilization. The motion estimation processor is implemented using TSMC 0.25 μm 1-poly 5-metal CMOS technology, which occupies a silicon area of 3.37x3.37mm~2 and operates at 110MHz. Experimental results show that it is able to estimate texture motion vectors of MPEG-4 AS profile in ITU-R601 format (720x480@30Hz/NTSC or 720x576@25Hz/ PAL) in real-time at around 90MHz.