The advent of deep sub-micron technologies has created a number of problems for existing design methodologies. Most prominent among them is the problem of timing closure, whereby design time is dramatically increased due to iterations between gate-level synthesis and physical design. It is well known that the heart of this problem lies in the use of wireload models based on wirelength statistics from legacy designs. Some technology projections in have suggested that wireload models will remain effective to block sizes on the order of 50k gates. This suggests that synthesis will not have to be changed much since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on production designs show that the problem is not quite so straightforward, and the efficacy of synthesis using wireload models depends upon technology data as well as specific characteristics of the design. We analyze these effects and dependencies in detail in this paper, and draw someconclusions about the amount of physical information that is required for synthesis to be effective. Finally, we discuss the implications on hierarchical design flows, and propose a solution via physical prototyping.
深亚微米技术的出现给现有的设计方法带来了许多问题。其中最突出的是时序收敛问题,由于门级综合和物理设计之间的迭代,设计时间大大增加了。众所周知,此问题的核心在于使用基于旧式设计的线长统计信息的线载模型。其中的一些技术预测表明,线载模型将仍然有效地阻止约5万门的块大小。这表明合成不必作太多更改,因为这大约是逻辑合成有效的最大大小。但是,我们对生产设计的分析表明,问题并不是那么简单,使用线载模型进行综合的效果取决于技术数据以及设计的特定特征。我们在本文中详细分析了这些影响和依赖性,并得出了一些有关有效合成所需的物理信息量的结论。最后,我们讨论了对分层设计流程的影响,并通过物理原型提出了解决方案。 P>
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