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Timing-driven placement based on monotone cell ordering constraints

机译:基于单调电池排序约束的时序驱动的放置

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In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.
机译:在本文中,我们介绍了一种新的时序驱动的放置算法,该算法试图将Zigzags和acrossses最小化在电路的时序关键路径上。我们观察到大多数路径,导致电路中的时序问题在路径的开始和结束节点的最小边界框之外。为了限制这种不良行为,我们对放置问题的物理限制,即,我们为电路中的每个关键路径分配优选的信号方向。从初始放置解决方案开始,通过使用基于移动的优化策略,这些优选的方向力强制电池在最大化新放置解决方案中最大化时序关键路径的单调行为的方向上移动。为了使方向分配易于进行,我们将所有电路路径均匀地将所有电路路径分组到一组输入输出导管中,并为每个这样的导管分配唯一的优选方向。我们将此想法整合到基于递归的双层型放置框架中,具有敏感的目标函数。一组标准放置基准测试结果表明,这种方法可提高所有基准电路的最先进的工业放置工具的结果,同时通过可容忍的量增加线长度。

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