Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing chip size. To address this problem instead of placing all systems components in one layer (i.e. in 2-D space) one can use a stack of single layer monolithic ICs (called here a 2.5-D integrated IC). To assess the potential benefits of such a 2.5-D integration schema this paper compares wire length distributions, obtained for 2-D and 2.5-D implementations of benchmark circuits. In the assessment two newly developed floorplanning and placement tools were used. Significant reductions in both total wirelength and worst-case wirelength was observed for the systems implemented as 2.5-D ICs.
机译:用于高密度神经传感微系统的高级2.5D异构集成包装
机译:改进的多项式混沌离散化方案,可将互连集成到设计环境中
机译:低k / Cu互连制造的高深宽比硬掩模方案技术进行工艺集成的可行性研究
机译:2.5维系统集成方案的互连特性
机译:2.5-D系统集成:设计角度。
机译:为神经元模型中的微分方程系统自动选择合适的积分方案
机译:改进的多项式混沌离散化方案,可将互连集成到设计环境中
机译:加速器系统串测试中互连区域的多层绝缘:一种新的设计和安装桥方案的实用工程方法