ESD Protection Design by Using Only 1脳VDD Low-Voltage Devices for Mixed-Voltage I/O Buffers with 3脳VDD Input Tolerance

摘要

A new electrostatic discharge (ESD) protection design by using only 1脳VDD low-voltage devices for mixed-voltage I/O buffer with 3脳VDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-驴m CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3脳VDD input tolerance.