Test methodology for Freescale's high performance e600 core based on PowerPC/spl reg/ instruction set architecture

摘要

This paper presents the DFT techniques used in Freescale's high performance e600 core. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 98% stuck-at-fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor.