A CMOS, self-biasing, single-supply op amp for low-voltage, high-gain applications is presented. The two-stage op amp includes a transimpedance building block used as a composite load for the input stage. The dc gain of the stage is substantially enhanced thanks to the very high output resistance of the active load. The building block is designed with regulated cascode components and, for bias stabilisation, a technique of replica bias sensing and common-mode feedback. This technique allows the supply voltage lowering to about (2|V/sub T/|+2|V/sub dc, out/|), which determines the minimum supply voltage of the op amp. At V/sub dd//spl ges/1.8 V, major performances of the op amp are: A/sub dc/<115 dB, f/sub T/=9 10/sup 6/ Hz, S/sub R/=8 V//spl mu/s, P/sub dis/=0.55 mW.
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机译：提出了一种适用于低压，高增益应用的CMOS，自偏置，单电源运算放大器。两级运算放大器包括一个跨阻构建模块，用作输入级的复合负载。由于有源负载的极高输出电阻，该级的直流增益得到了显着提高。该构件的设计采用可调节的共源共栅元件，并且为了实现偏置稳定，采用了复制偏置感应和共模反馈技术。此技术可使电源电压降低到大约（2 | V / sub T / | +2 | V / sub dc，out / |），从而确定运算放大器的最小电源电压。在V / sub dd // splges / 1.8 V时，运算放大器的主要性能为：A / sub dc / <115 dB，f / sub T / = 9 10 / sup 6 / Hz，S / sub R / = 8 V / spl mu / s，P / sub dis / = 0.55毫瓦。
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