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DSP-based clock recovery implemented in a field programmable gate array

机译:在现场可编程门阵列中实现的基于DSP的时钟恢复

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In data communication systems, a clock signal is normally extracted from the received data so that the data can be properly decoded. The baseband coding scheme may be chosen so that the data contains a strong spectral component at the desired clock rate. Such codes are termed "self clocking". A phase locked loop (PLL) may be used to recover the clock signal from the data, but loss of lock and synchronisation can occur if the data "fades" for a period of time. Problems can also occur in regaining lock if the received data are poor and this results in lost data. Also, in order to ensure that the PLL is in a locked condition before data are received a long synchronising sequence must be applied before the data can be accurately clocked. A DSP clock recovery scheme exploits the feature of a long impulse response in an IIR (infinite impulse response) filter, when the poles are close to the unit circle. In the context of clock recovery this feature is desirable since it can be exploited to provide a good flywheel effect over periods of lost input, i.e. a fade.
机译:在数据通信系统中,通常从接收到的数据中提取时钟信号,以便可以正确解码该数据。可以选择基带编码方案,以使数据在所需的时钟速率下包含较强的频谱分量。这样的代码被称为“自计时”。锁相环(PLL)可用于从数据中恢复时钟信号,但是如果数据在一段时间内“淡入淡出”,则会发生锁定和同步丢失的情况。如果接收到的数据很差,则在重新获得锁定时也会出现问题,从而导致数据丢失。同样,为了确保在接收数据之前PLL处于锁定状态,必须采用长同步序列,然后才能对数据进行精确计时。当极点靠近单位圆时,DSP时钟恢复方案利用IIR(无限脉冲响应)滤波器中的长脉冲响应的功能。在时钟恢复的情况下,此功能是理想的,因为可以利用它在输入丢失(即衰落)期间提供良好的飞轮效果。

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