Contribution of interface states and bulk traps to GaAs MIS admittance

摘要

Measurements of Au/Ti/Pd-SiO_2-n-GaAs structure characteristics have revealed two maxima of normalized MIS conductance vs. frequency and large frequency dispersion of MIS capacitance. The position of one maximum is dependent on gate voltage and the second is not dependent on a bias. A model of insulator-semiconductor interface as a disordered system with interface states distributed in energy and in space including the presence of semiconductor bulk traps allows us to describe these characteristics. The possibility of separating the interface state contribution and bulk trap contribution have been presented and their parameters estimated.