FPGA based digital receiver and timing generator for modern radars

摘要

This paper discusses the design and implementation of FPGA based Octa-channel digital receiver for radar applications with higher sampling rate, better SNR performance and inter channel isolation. This 16 layer metal core PCB is capable of performing Signal processing algorithms for eight channels which includes Digital Down Conversion, Digital Pulse Compression, Moving Target Indicator, Fast Fourier Transform and 2D-Constant False Alarm Rate. Extracted plot reports are transferred to the Radar Data Processing Unit using a 6.25Gbps Aurora interface. This module also takes care of complete radar timing generation and distribution to various subsystems. The distinctive features of this digital receiver are high speed ADC-QDR interface with FPGA and 10Gbps compatible hybrid PCB design.