Performance/Energy Efficiency Analysis of Register Files in Superscalar Processors

摘要

This paper evaluates the energy consumption in register files for its different configurations and then assesses the affect of those configurations on the performance of a superscalar processor, and thus analyzes the feasibility of increasing the issue width to gain performance from energy's perspective. An execution driven, cycle accurate performance simulator- simplescalar has been used to generate IPC and register file access information for three different SPECint-95 benchmarks for various machine configurations. From the obtained data, performance/energy (IPC per unit mJ) efficiency for the various register file configurations was calculated and analyzed to suggest most energy efficient register file structures. The variation of performance/energy efficiency has been studied on component level to provide interesting cues for its improvement. We also analyze the per access read/write energy spent in different register file components for different possible configurations to figure out the variation of energy in components as the register file size (number of ports and number of registers) are varied. Further, we also study the behavior of total read and write accesses from shadow and architectural register files, which could be used to develop compiler techniques for low power.