Design Safe Interface Circuit for VXIbus Device

摘要

When designing the interface circuit of the VXIbus device with state machines, combined circuit and sequence circuit, the unexpected glitches will happen between the different parts in the CPLD. It will lead the system to metastability. The reasons, which bring the circuit to metastability, are analyzed in this paper. Then some processes are introduced to reduce the glitch. By the help of optimization design and synchronous circuit design, the capability of fault-tolerance for state machine is improved. Adopting global clock, the output and input logic are fully control by the rising edge or falling edge of the same clocking signal. For the reset signal and the clear signal, the circuit design involve with Flip-Flop and feedback signal of them. The signals are guaranteed to be always glitch free and the probability of accessing into dead states is reduced. The circuit will run more reliable than before.